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digitally programmable 8 to 25 multiplex lcd controller & driver features n slim ic for chip-on-board, with gold bumps for chip-on-glas and chip-on-flex technologies n very simple 2-wire interface n digitally programmable multiplex rates: 8 x 113, 9 x 112, 16 x 105, 17 x 104, 20 x 101, 21 x 100, 24 x 97, 25 x 96 n no lost pads while row driver from 8 up to 25 n on chip: volt age mul ti plier,v lcd up to 7 v (3 to 6 v at 25 c), 64 v lcd dig i tally pro gram ming steps, 4 v lcd tem per a ture com pen sa tion fac tors, bias gen er a tion, v on / v off gen er a tion, frame fre quency, dis play re fresh ram n no busy state n high noise immunity in inputs n no external components needed, except a v lcd capacitor n digitally reversing row data n digitally reversing column data n inverting data function n blank func tion n set function n checker and inverted checker functions n sleep modes n low lcd operating current consumption n wide v dd volt age sup ply range, 2 to 5 v n wide temperature range: -40 to + 85 c n direct display of ram data through the display data ram (to cas cade ics, please see fig. 19 and con tact em-marin.) de scrip tion the EM6124 is a low power cmos lcd con trol ler and driver. the 8, 16, 20 and 24 way mul ti plex are dig i tally pro - gram ma ble by the com mand byte. one ad di tional line can be added for icons or in verted video by pro gram ming 9, 17, 21 or 25 way mul ti plex. the dis play re fresh is han dled on chip by an in ter nal rc os cil la tor via one selectable 25 x 116 ram which holds the lcd con tent driven by the driver. lcd pix els (or seg ments) are ad dressed on a one to one ba sis with the 25 x 116 bit ram (a set bit cor re - sponds to an ac ti vated lcd pixel). the EM6124 has very low dy namic cur rent con sump tion, typ i cally 70 a at v dd = 2 v, v lcd = 7 v mak ing it par tic u larly at trac tive for por ta - ble and bat tery pow ered prod ucts. the wide op er at ing range on sup ply volt ages and tem per a ture of fers much ap pli ca tion flex i bil ity. the lcd volt age, bias gen er a tion and frame fre quency are gen er ated on chip. the clock sig nal can be used to shift and to latch the data into the ram. ap pli ca tions n mobile phones (gsm, dect) n smart cards n automotive displays n por ta ble, bat tery op er ated prod ucts n bal ances and scales, util ity me ters 1 EM6124 em microelectronic-marin sa pad assignment typical operating configuration EM6124 fig. 1 fig. 2 (to con tact power sup plies, please see fig. 20.)
ab so lute max i mum rat ings parameter symbol conditions sup ply volt age range v dd1,2 -0.3 v to 6 v sup ply high volt age range v hv -0.3 v to 6 v internal generated v lcd v lcd 7 v volt age at di, do, clk, fr, res v logic -0.3 v to v dd +0.3 v volt age at s1 to s121 v disp -0.3 v to v lcd +0.3 v stor age tem per a ture range t sto -65 to +150 c elec tro static dis charge max. to mil-std-883c method 3015 v smax 1000 v max i mum sol der ing con di tions t smax 250 c x 10 s ta ble 1 stresses above these listed max i mum rat ings may cause per ma nent dam age to the de vice. ex po sure be yond spec i fied op er at ing con di tions may af fect de vice re li abil ity or cause mal func tion. han dling pro ce dures this de vice has built-in pro tec tion against high static volt - ages or elec tric fields; how ever, anti-static pre cau tions must be taken as for any other cmos com po nent. un less oth er wise spec i fied, proper op er a tion can only oc cur when all ter mi nal volt ages are kept within the sup ply volt - age range. un used in puts must al ways be tied to a de - fined logic volt age level. op er ating con di tions parameter symbol min. typ. max. unit operating temperature t a -40 +85 c logic supply voltage v dd1,2 2 3 5.5 v supply high voltage v hv 2.5 3 5.5 v ta ble 2 2 EM6124 electrical characteristics v dd1 = v dd2 = 3 v, v hv = 2.5 to 5 v, and t a = -40 to +85 c, un less oth er wise spec i fied pa ram e ter sym bol test con di tions min. typ. max. units standby sup ply cur rent i dd see note 1) 6 13 a standby sup ply cur rent i hv see note 1) , v lcd step 30 (hexa) 65 170 a dynamic supply current i dd see note 2) 50 75 a standby supply current i hv see note 3) , v lcd step 00 (hexa) 35 140 a sleep mode supply current i dd 0.1 a sleep mode supply current i hv 0.1 a con trol sig nals di, clk, fr, res1,res2 in put leak age i in v dd1,2 or v ss -1 1 a in put ca pac i tance c in at t a = 25 c 8 pf low level in put volt age v il 0 0.3 v dd1,2 v high level in put volt age v ih 0.7 v dd1,2 v dd1,2 v dc output component vdc see table 4 30 100 mv v lcd (internally generated) v lcd see note 4) 6.15 v lcd v lcd see note 5) 3 to 7 v v lcd step 66 mv 1) all out puts open, di and clk at v ss , mux ra tio = 24, checker pat tern. ta ble 3 2) all out puts open, di at v ss , f clk = 1 mhz, mux ra tio = 24, checker pat tern. 3) di and clk at v ss , checker pat tern, mux ra tio = 8. 4) ini tial iza tion bits 18 to 23 = 110000 and ini tial iza tion bits 10, 11 = 00; la ser trim ming on re quest. 5) ini tial iza tion bits 18 to 23 = 000000/111111. dc output component output frame logic data measured* guaranteed n 0l | v lcd - v 1 | v 1 = 0.83 x v lcd 100 mv row driver n + 1 0l | v 4 - v ss | v 2 = 0.66 x v lcd 100 mv 0l | v lcd - v 2 | v 3 = 0.34 x v lcd 100 mv column driver n + 1 0l | v 3 - v ss | v 4 = 0.17 x v lcd 100 mv v x ( load = +1 a) + v x (load = -1 a) *v x = 2 , mux 24 or 25 pro grammed, v lcd = 6 v, t a = 25 c. test is per formed for mul ti plex rate = 25. all mul ti plex rate 1 25 are guar an teed by de sign. if mul ti plex rate 1 25, test will be per formed on re quest. ta ble 4
EM6124 3 timing characteristics v dd1 = v dd2 = 2 to 3 v, v hv = 2.5 to 5 v, and t a = -40 c to +85 c parameter symbol test conditions min. typ. max. units clock high pulse width t ch 70 ns clock low pulse width t cl 110 ns clock period t per 550 ns reset 1 pulse width t res1 10 s reset 2 pulse width t res2 130 ns clock and fr rise time t cr 200 ns clock and fr fall time t cf 200 ns data input setup time t ds 20 ns data input hold time t dh 260 ns fr (internal frame frequency) f fr 1) 75 hz 1) EM6124 (n), fr = n times the de sired lcd re fresh rate where n is the EM6124 mux mode num ber; ta ble 5a la ser trim ming on request. see fig. 17.01 and 17.02 for more de tails con cern ing the frame fre quency v dd1 = v dd2 = 3 to 5 v, v hv = 2.5 to 5 v, and t a = -40 c to +85 c parameter symbol test conditions min. typ. max. units clock high pulse width t ch 50 ns clock low pulse width t cl 55 ns clock period t per 350 ns reset 1 pulse width t res1 10 s reset 2 pulse width t res2 80 ns clock and fr rise time t cr 200 ns clock and fr fall time t cf 200 ns data input setup time t ds 20 ns data input hold time t dh 140 ns fr (internal frame frequency) f fr 1) 75 hz 1) EM6124 (n), fr = n times the de sired lcd re fresh rate where n is the EM6124 mux mode num ber; ta ble 5b la ser trim ming on re quest. timing waveforms fig. 3
EM6124 pin assignment name function s1...s121 lcd outputs, see fig.4 fr ac i/o signal for lcd driver output di serial data input do serial data output clk data clock input res1 general reset res2 reset the serial interface counter v lcd internal generated voltage output v dd1 power supply for logic v dd2 power supply for analogic v hv power supply for high voltage v ss supply gnd ta ble 9 1 bit interface description this 1 bit in ter face is very sim ple to use. there are three modes to load data into the EM6124. com mand byte only mode to validate this mode, 8 bits must be shifted with bit 3 to bit 7 setted to 1l. this mode is used for blank, set or sleep mode func tions. com mand byte and ini tial iza tion mode to validate this mode, 32 bits must be shifted with bit 0 and bit 1 setted to 1l. bit 2 (sleep) can be ac tive or in ac tive. bit 3 to bit 7 (ram ad dress) can be in any state but it is im por - tant that they are not all si mul ta neously setted to 1l, oth er - wise the chip will be in com mand byte only mode. com mand byte and dis play in for ma tion mode to validate this mode, 128 bits must be shifted, eight first bits are for com mand byte, all the other are ram data de - pend ing of col bit mode and mul ti plex ra tio. there are also x bits don?t care in each load ing de pend ing on the programmation of the chip (see fig. 4 for more de tails). in each ram?s data load ing, the com mand byte has to be in tro duced for the ram ad dress. be fore load ing any data into the ram the chip has to be in i tial ized. com mand byte commmand bits 0 to 7 0 1 2 3 4 5 6 7 blank set sleep ram ad dress ta ble 6 cmdbit 0 : blank bit forces all col umn out puts off. cmdbit 1: set bit forces all col umn out put on. note: if bit 0 and bit 1 are both to 1l, the chip will be in ini tial - iza tion mode. see re marks be low. cmdbit 2 : sleep mode bit, stops the volt age booster and the in ter nal os cil la tor, ac tive bit col forces all out puts to v ss . cmdbits 3-7 : ram ad dress bits. see ta ble 6. if cmdbits 3-7 are set to 1l, EM6124 is in cmd byte only mode. initialization bits ini tial iza tion bits 8 to 15 8 9 10 11 12 13 14 15 mux mode temp. coeff. checker inv.checker col inv.row ini tial iza tion bits 16 to 23 16 17 18 19 20 21 22 23 m/ lsb video step 1 step 2 step 3 step 4 step 5 step 6 ini tial iza tion bits 24 to 31 24 25 26 27 28 29 30 31 icon sleep 2 test 6 test 5 test 4 test 3 test 2 test 1 ta ble 7 mux ra tio (init. bit 8, 9) 8 9 mux mode 0 0 8 0 1 16 1 0 20 1 1 24 ta ble 8 init.bit 8-9: mux mode bits. the mul ti plex ra tio is se lected by these two bits. ta ble 8 shows the cor re spond ing val ues. init.bit 10-11 : v lcd tem per a ture co ef fi cient is se lected by these t wo bits. ta ble 11 shows the cor re spond ing val ues. i nit.bit 12 : checker bit gives the pos si bil ity to force all out puts seg ments in checked form (see fig. 10 and fig. 18.14). init.bit 13 : in verse checker bit gives the pos si bil ity to force all out puts seg ments in in verse checked form (see fig. 10 and fig. 18.15). init.bit 14 : col bit configures the EM6124 on row and col umn driver or col umn driver only. in this mode the frame fre quency must be ex ter nal. init.bit 15 : row in ver sion, pos si bil ity to in verse the or der of the row out puts (see ta ble 10 and fig. 18.12). init.bit 16 : m/ lsb , pos si bil ity to in verse the or der load ing for ram data (see fig. 4). init.bit 17 : video bit, pos si bil ity to in verse the con tent of the ram. all the 0l pass to 1l and all the 1l pass to 0l (see fig. 18.11). init.bit 18-23 : v lcd 64 steps programmation bits. see fig. 8. bit 18 (step 1) for msb and bit 23 (step 6) for lsb. init.bit 24 : icon bit adds one line more to the se lected mux mode ra tio for icon seg ments out puts. init.bit 25 : sleep 2. set all out puts at v ss . init.bit 26-31 : must be setted to 0l. re set 1 power-up : must be fol lowed by a reset cy cle. after the re set 1 pulse the lcd con trol ler driver is set to the fol low - ing sta tus: - all out puts at v ss - blank & set (cmdbits 0,1) = 0l - sleep mode (cmdbit 2) = 0l - ram ad dress (cmdbits 3 to 7) = 0l - mul ti plex ra tio (init.bits 8, 9) = 0l - tem per a ture co ef fi cient (init.bits 10,11) = 0l - checker & inv.checker (init.bits 12, 13) = 0l - col mode (init.bit 14) = 1l - inv. row (init.bit 15) = 0l - m/ lsb (init.bit 16) = 1l - video (init.bit 17) = 1l - v lcd step (init.bits 18 to 23) = 0l - icon (init.bit 24) = 0l - sleep 2 (init.bit 25) = 1l - the con tent of the ram re mains un changed an ini tial iza tion should take place af ter re set (32 bits sent). 4
5 EM6124 data transfer cycle fig. 4
EM6124 6 fig. 5 in this mode only 8 bits have to be shifted into the EM6124 with ad - dress bits to logic 1. command byte and initialization mode time in this mode only 32 bits have to be shifted into the EM6124 with bits blank and set to logic 1. fig. 6 command byte and display information mode this mode needs 128 bits shifted into the EM6124. do not in tro duce one of the two codes which were de scribed above. (all ad dress bits to logic 1 or blank and set bits to 1 si mul ta neously) fig.7 out put row assignments mux mode row ram ad dress mux 8 mux 8 mux 16 mux 16 mux 20 mux 20 mux 24 mux 24 + icon + icon + icon + icon inv. row inv. row inv. row inv. row inv. row inv. row inv. row inv. row bit 3 bit 4 bit 5 bit 6 bit 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 s1 s16 s1 s17 s1 s20 s1 s21 s1 s22 s1 s23 s1 s24 s1 s25 2 0 0 0 0 1 s2 s15 s2 s16 s2 s19 s2 s20 s2 s21 s2 s22 s2 s23 s2 s24 3 0 0 0 1 0 s3 s14 s3 s15 s3 s18 s3 s19 s3 s20 s3 s21 s3 s22 s3 s23 4 0 0 0 1 1 s4 s13 s4 s14 s4 s17 s4 s18 s4 s19 s4 s20 s4 s21 s4 s22 5 0 0 1 0 0 s13 s4 s13 s13 s5 s16 s5 s17 s5 s18 s5 s19 s5 s20 s5 s21 6 0 0 1 0 1 s14 s3 s14 s4 s6 s15 s6 s16 s6 s17 s6 s18 s6 s19 s6 s20 7 0 0 1 1 0 s15 s2 s15 s3 s7 s14 s7 s15 s7 s16 s7 s17 s7 s18 s7 s19 8 0 0 1 1 1 s16 s1 s16 s2 s8 s13 s8 s14 s8 s15 s8 s16 s8 s17 s8 s18 9 0 1 0 0 0 s17 s1 s13 s8 s13 s13 s9 s14 s9 s15 s9 s16 s9 s17 10 0 1 0 0 1 s14 s7 s14 s8 s10 s13 s10 s14 s10 s15 s10 s16 11 0 1 0 1 0 s15 s6 s15 s7 s13 s10 s13 s13 s11 s14 s11 s15 12 0 1 0 1 1 s16 s5 s16 s6 s14 s9 s14 s10 s12 s13 s12 s14 13 0 1 1 0 0 s17 s4 s17 s5 s15 s8 s15 s9 s13 s12 s13 s13 14 0 1 1 0 1 s18 s3 s18 s4 s16 s7 s16 s8 s14 s11 s14 s12 15 0 1 1 1 0 s19 s2 s19 s3 s17 s6 s17 s7 s15 s10 s15 s11 16 0 1 1 1 1 s20 s1 s20 s2 s18 s5 s18 s6 s16 s9 s16 s10 17 1 0 0 0 0 s21 s1 s19 s4 s19 s5 s17 s8 s17 s9 18 1 0 0 0 1 s20 s3 s20 s4 s18 s7 s18 s8 19 1 0 0 1 0 s21 s2 s21 s3 s19 s6 s19 s7 20 1 0 0 1 1 s22 s1 s22 s2 s20 s5 s20 s6 21 1 0 1 0 0 s23 s1 s21 s4 s21 s5 22 1 0 1 0 1 s22 s3 s22 s4 23 1 0 1 1 0 s23 s2 s23 s3 24 1 0 1 1 1 s24 s1 s24 s2 25 1 1 0 0 0 s25 s1 ta ble 10 time time command byte only mode
EM6124 7 temperature control due to the tem per a ture de pend ency of liq uid cristals vis - cos ity the lcd con trol ling volt age v lcd must be in creased for lower tem per a tures to main tain op ti mal con trast. the EM6124 is avail able with 4 dif fer ent tem per a ture co ef fi - cients (see fig. 9). the co ef fi cient is se lected by 2 bits in the ini tial iza tion code tc bits 10 and 11. ta ble 11 shows the typ i cal val ues of the dif fer ent tem per a ture co ef fi cients. they are pro por tional to the pro grammed v lcd . typical values of the tem per a ture co ef fi cients bit 10, bit 11 value unit 0 0 +0.18 x v lcd mv/c 0 1 - 0.27 x v lcd mv/c 1 0 -1 x v lcd mv/c 1 1 -1.7 x v lcd mv/c ta ble 11 checker and checker inverse a fast check dis play can be eas ily cre ated set ting initialization bits 12 and 13 (called ?checker? and ?inv. checker?). the dis play is com pletely checked with only 2 ini tial iza tion se quences, one ?checker? and one ?inv. checker?. for checker, the pat tern fills the dis play with al - ter nately on and off pix els as shown in fig. 10. for inv. checker, ev ery thing is in verted (see fig.18.14 and 18.15). pat tern of checker mode typical v lcd programming temperature coefficients fig. 9 fig. 8 fig. 10 internally generated v lcd versus temperature fig. 11
8 EM6124 display functions bit s tate logic 0 logic 1 8 - 9: mux mode see ta ble 8 10 -11:temp.coeff. see ta ble 11 12: checker in ac tive chess dis play 13: inv. checker in ac tive in verse chess dis play 14: col colum driver only row and col umn driver 15: inv. row in cre ment rows dec re ment rows (ex am ple for mux 24: (ex am ple for mux 24: row 1, 2, 3, ... , 24, 1, 2, ...) row 24, 23, 22, ... ,2 ,1, 24, 23, ...) 16: m/ lsb loading in lsb mode loading in msb mode 17: video in verse con tent of ram in ac tive 18 - 23: v lcd step see fig. 8 24: icon in ac tive add one line more to seledted mux mode 25: sleep in ac tive all out puts at v ss 26 - 31: must be at 0l ta ble 12
EM6124 9 block diagram fig. 12
EM6124 10 lcd voltage bias levels lcd drive type lcd bias con fig u ra tion v op v off (rms) v on (rms) v off (rms) ta ble 13 optimum lcd bias voltages multiplex v lcd v1 v2 v3 v4 v ss rate 1 : 24 1 0.830 0.660 0.340 0.170 0 1 : 20 1 0.817 0.634 0.366 0.183 0 1 : 16 1 0.800 0.600 0.400 0.200 0 1 : 8 1 0.750 0.500 0.250 - 0 v lcd > v1 > v2 > v3 > v4 > v ss the val ues in the above ta ble are given in ref er ence to v lcd e.g. 0.5 means 0.5 x v lcd ta ble 14 1/5 bias 6 levels 1/4 bias 5 levels EM6124 (24) EM6124 (20) EM6124 (16) EM6124 (8)
EM6124 11 row and column multiplexing waveform EM6124 (8) v op = v lcd ? v ss , v state = v col ? v row fig. 13
EM6124 12 row and column multiplexing waveform EM6124 (16) v op = v lcd ? v ss , v state = v col ? v row fig. 14
EM6124 13 row and column multiplexing waveform EM6124 (20) v op = v lcd ? v ss , v state = v col ? v row fig. 15
EM6124 14 row and column multiplexing waveform EM6124 (24) v op = v lcd ? v ss , v state = v col ? v row fig. 16
EM6124 15 functional description supply voltage v dd1 , v dd2 , vh v , v lcd , v ss the volt age be tween v dd1 and v ss is the sup ply volt age for the logic and the in ter face. the volt age be tween v dd2 and v ss is the sup ply volt age for the analogic. v dd1 and v dd2 must be the same volt age and, in or der to guar an tee the best func tion ing, v dd1 and v dd2 have to be sep a rately con - nected to the pcb (see fig. 19). the volt age v lcd is in ter - nally gen er ated for the sup ply volt age of the lcd and is used for the gen er a tion of the in ter nal lcd bias level. an ex ter nal ca pac i tor of 1 f must be con nected be tween v lcd and v ss . ta ble 15 shows the re la tion ship be tween v1, v2, v3, v4 for a pro grammed mul ti plex rate. note that v lcd > v1 > v2 > v3 > v ss for the EM6124 8 mux pro - grammed, and for the EM6124 16, 20, 24 mux pro - grammed v lcd > v1 > v2 > v3 > v4 > v ss . the volt age be tween v hv and v ss is the sup ply volt age for high volt age part of the EM6124. an ex ter nal v lcd may also be used by con nect ing a power sup ply and pro gram ming a lower v lcd volt age dur ing ini tial iza tion. data in put the data in put pin, di, is used to load se rial data into the EM6124. the nor mal se rial data word length is128 bits. 32 and 8 bits are also avail able in a spe cial mode (see 1 bit in ter face de scrip tion). the com mand byte is loaded first and then the seg ment data bits (see fig. 4). res1 in put re set is ac com plished by ap ply ing an ex ter nal res1 pulse (ac tive low). when re set oc curs within the spec i fied time, all in ter nal reg is ter are re set how ever the con tent of the ram is still un changed. the state af ter re set is de - scribed on page 4. res2 input re set is ac com plished by ap ply ing an ex ter nal res2 pulse (ac tive low). when re set oc curs within the spec i fied time, the in ter nal coun ter for se rial in ter face is re set. the coun ter of the serial in ter face for data inputs is ready for a new load ing of data. this re set 2 does not change the con tent of the ram nei ther the con tent of the com mand and the ini tial iza tion bits. to avoid trou ble in case of soft - ware in ter rupt of the mpu dur ing data load ing, this func - tion can be used. power-up on power up the data in the shift reg is ters, the dis play ram, the se quencer driv ing the 8/16/20/24 rows and the 121 bit dis play latches are un de fined. clk in put the clock in put is used to clock the di se rial data into the EM6124. fr in put / output the frame fre quency is re al ized by an in ter nal os cil la tor with a typ i cal value of 75 hz. the in ter nal row fre quency changes with the num ber of rows ( f row = 75 x n, where n = 8, 16, 20, 24). when bit 14 ( col ) is in ac tive (ac tive low), the frame fre quency is given by the in ter nal os cil la tor. this fre quency can be mea sured on the i/o fr. when bit 14 ( col ) is ac tive (ac tive low), the frame fre quency is ex ter nal then the fre quency is given di rectly by the fr in put to the row and col umn driver (see fig. 16 and 17 for more de - tails con cern ing the frame fre quency). driver out puts s1 to s116 there are 121 lcd driver out puts on the EM6124. the out - put as sign ments de pend on the cho sen mux mode ra tio (init. bits 8, 9) and the col func tion (init. bit 14). when init. bit 14 (col) is ac tive, all 116 out puts func tion as col umn driv ers. ta ble ?out put row as sign ments? and fig. 4 de scribe ex actly the cor re spon dent data to the out put of the chip. there is one to one re la tion ship be tween the dis - play ram and the lcd driver out puts. each pixel (seg - ment) driven by the EM6124 on the lcd has a dis play ram bit which cor re sponds to it. set ting the bit turns the pixel ?on? and clear ing it turns ?off?. for chip-on-glass better per for mances can be ob tained by cov er ing the back - side of the chip. typical frame frequency at v dd = 3 v typical frame frequency at t a = 25 c fig.17.01 fig.17.02
16 EM6124 application example these ta bles/fig ures show how to use the EM6124 with a given ini tial iza tion. rows ?data? show the log i cal value to af fect pad di for each fall ing edge of pad clk. a re set cy cle pad res1 at ol is re quired be fore send ing dat a. fig. 18.01 fig. 18.02 ta ble 15 (con tin ued on next pages)
17 EM6124 application example continued fig. 18.03 fig. 18.04 fig. 18.05
18 EM6124 application example continued fig. 18.06 fig. 18.07 fig. 18.08
19 EM6124 application example continued fig.18.09 fig.18.10 fig.18.11
20 EM6124 application example continued fig. 18.12 fig. 18.13 fig. 18.14
EM6124 21 application example continued fig. 18.17 fig. 18.16 fig. 18.15
22 EM6124 contacting power supply EM6124 fig. 20 in or der to guar an tee the best func tion ing v dd 1 and v dd 2 have to be con nected separtely on the pcb, if pos si ble. applications two EM6124 work in parallel to drive up to 50 rows x 96 columns or 25 rows x 212 columns as below EM6124 EM6124 fig. 19 by con nect ing the v lcd bias outputs as shown, the pixel load is av er aged across all the driv ers. the ef fec tive bias level source im ped ance is the par al lel com bi na tion of the to tal num ber of driv ers. * v dd1 and v dd2 have been con nected to gether.
EM6124 23 package and ordering information dimensions of chip form and bumped die fig. 21 em mi cro elec tronic-marin sa can not as sume any re spon si bil ity for use of any cir cuitry de scribed other than en tirely em bod ied in an em mi cro elec tronic-marin sa prod uct. em mi cro elec tronic-marin sa re serves the right to chan ge the cir cuitry and spec i fi ca tions with - out no tice at any time. you are strongly urged to en sure that the in for ma tion given has not be en su per seded by a more up-to-date ver - sion. e. & o.e. printed in swit zer land, th ? 2000 em mi cro elec tronic-marin sa, 01/2000, vers. b/294 em mi cro elec tronic-marin sa, ch - 2074 marin, swit zer land, tel. (+41) 32 - 755 51 11, fax (+41) 32 - 755 54 03 all di men sions in mi cron thick ness: 15 mils bump size: lcd out put pads = 50 x 100 mi cron, in put/out put pads = 102 x 102 mi cron bump height: 17.5 mi cron bump hard ness: 50 vickers chip size: [x x y] 7930 x 1493 mi cron or 312 x 59 mils note: the or i gin (0,0) is the lower left co or di nate of cen ter pads. the lower left cor ner of the chip shows dis tances to or i gin. ordering information the EM6124 is avail able in the fol low ing pack ages: chip form EM6124 chip* bumped form EM6124 bumped when or der ing please spec ify the com plete part num ber and pack age. * on request

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